CHE programming of electrically erasable programmable read-only memories (EPROMs) and flash EPROMs can generate between 50 .mu.A-100 .mu.A of cell current. For state of the art devices, which are often built onto P-type epitaxial layers over a low resistivity substrate, this substrate current sinks into the low resistivity layer and does not generate significant voltage drop. However, for EPROMs and flash EPROMs that use a non-epitaxial layer substrate, or ones that are built on an isolated P-well surrounded by a deep N-well, such as in a triple well process, the substrate current that is generated during programming can build up large voltage drops across the resistive FAMOS P-well region.
If voltage drop exceeds the diode turn-on voltage of approximately 0.7 volts, then the source junction will forward bias. This problem of the resistive P-well situation may be seen in a lowering of the floating-gate avalanche-injection metal oxide semiconductor (FAMOS) BVCEO voltage value. Lowering the BVCEO values, unfortunately, reduces the maximum drain potential of the device. For a constant current programming load line, this reduces the gate current and degrades programmability of the EPROM or flash EPROM.
FIGS. 1 and 2 show the adverse effects of lower and BVCEO voltage values. In particular, FIG. 1 illustrates a plot of two BVCEO characteristic lines for a flash EPROM cell built over a triple well structure that includes an isolated P-well within a deep N-well. In the first case of line 10, the isolated P-well is well grounded and the deep N-well potential is at ground potential. The resistance R equals 15.OMEGA.. In the second case of line 12, the isolated P-well is simulated to be resistive at a value of 15 K.OMEGA.. Line 10 shows the shift in the BVCEO characteristic that yields a lowered programming voltage and generally degrades performance of the memory.
Another problem that arises when the substrate current builds up a voltage drop across the resistive FAMOS P-well is that once the source junction forward biases, it sprays electrons into the substrate. Some of the electrons will be collected by the drain junctions of the adjacent cells in the bit line stress mode. In this case, electrons entering the high electric field region near the drain create hot electron-holes pairs. Due to the polarity of the gate field near the drain, these hot electron-hole pairs are likely to be injected into the gate oxide and cause charge loss from the floating gate.
The table of FIG. 2 shows the effect of rising body potential on bit line stress. In the table of FIG. 2, the gate voltage, V.sub.g, equals zero; the drain voltage, V.sub.d, equals six volts; and the source voltage, V.sub.s, equals zero. Bit line stress occurs for approximately one second, in this example. The parameter, V.sub.b, represents the bins voltage across the resistive FAMOS P-well region. As the FIG. 2 table shows, with V.sub.b exceeding 0.7 volts, the threshold voltage, V.sub.t values of 0.10, 0.05, and 0.5 when V.sub.b was at or below 0.7 volts. The lowered V.sub.t, therefore, indicates the degraded programmability that breakdown of the source junction diode causes. Basically, as the substrate potential rises, the charge loss from floating gate rises correspondingly. This phenomenon exhibits an approximately exponential cause and effect relationship. Also, there is some expectation that the above-stated bit line stress mechanism causes grain degradation in flash memory devices as a result of the hot hole injection.
To avoid the above issues, the voltage drop in the substrate during programming should stay below the diode turn on voltage of approximately 0.7 volts. One way to achieve this result is to reduce the FAMOS P-well sheet resistance. Unfortunately, for triple well technology, this solution increases the process complexity. Therefore, there is a desire to build single isolated P-well to meet the CMOS requirements for negative voltage switching, and use the same isolated well for FAMOS devices. In this case, the high sheet resistance of the isolated P-well cannot meet the FAMOS requirements. For large arrays, the substrate bias build-up during programming forward biases the source junction and cause the above-stated device reliability concerns.
Other known solutions to this problem are process-oriented, using either a low-sheet-resistance FAMOS P-well or a very high energy implant. Both solutions, however, increase the process and the device-design complexities.